It is known to provide signal value storage circuitry, such as D-type flip-flops (DFF), for use in storing signal values, such as signal values representing binary values. Such signal value storage circuitry may be used in many different places within a data processing system, such as for storing data values to be processed, control values for controlling such processing, program instructions to control processing and the like.
It is known from WO-A-2004/084072 to provide a data processing system which is configured to operate at a finite non-zero error rate and includes error detection and recovery mechanisms. In this way, the operating frequency can be increased and/or the operating voltage reduced to a point at which errors occur, but that the overhead associated with recovering from those errors is less than the gain achieved by operating at the higher frequencies and/or lower voltages.
Within such systems it is known to provide DFFs which incorporate a transition detector on the data input and utilise a pulse generator or a clock chopping device to define an error detection window around an edge of the clock signal controlling the DFF. If a transition occurs in the input signal to the DFF after the signal has been captured into the DFF and during the error detection period, then this indicates a late arriving signal at the DFF and corresponds to an error that should trigger an error recovery operation.
A problem with this type of DFF is that the transition detector monitors the input of the master latch to observe the late arriving signal. To ensure a late input transition is successfully identified, there needs to be some margin between the set-up time that is used to flag such a late input transition and the minimum permitted set-up time of the DFF itself. Although it is desirable to keep this margin small to reduce the set-up time, it is important that the system detects set-up violations across the entire permitted range of process, temperature, operating voltage and the like. This margin adds directly to the characterised set-up time of the device, because under normal operating circumstances the condition is not expected to encounter any late input transitions. Various paths within the DFF employing this technique contribute to the uncertainty in the timing of its operation.
With this background, the increase in random variation in the performance characteristics of such devices as process nodes shrink has the result that yet more margin needs to be added to the timing to guarantee that late arriving signals are properly detected and flagged. All this increase in margin leads to a significant increase in the set up time of a DFF employing these error detection and correction techniques compared to the set up time of the underlying DFF not using such techniques. This is a significant performance penalty.